1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various hybrid fin cut etching processes for integrated circuit products that include both tapered and non-tapered FinFET semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially field effect transistors (FETs), are provided and operated on a restricted chip area. FETs come in a variety of different configurations, e.g., planar devices, FinFET devices, nanowire devices, etc. These FET devices are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
In contrast to a planar FET, which, as the name implies, is a generally planar structure, a so-called FinFET device has a three-dimensional (3D) structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device 10 includes three illustrative fins 14, a gate structure 16, a sidewall spacer 18 and a gate cap layer 20. A plurality of fin-formation trenches 22 are formed in the substrate 12 to define the fins 14. A recessed layer of insulating material 13 is positioned between the fins 14 in the areas outside of the gate structure, i.e., in the source/drain regions of the device 10. The gate structure 16 is typically comprised of a layer of gate insulating material (not separately shown), e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device 10. The fins 14 have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device 10 when it is operational, i.e., the gate length of the device 10. The portions of the fins 14 covered by the gate structure 16 are the channel regions of the FinFET device 10. The gate structures 16 for such FinFET devices 10 may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques. A FinFET device may have either a tri-gate or dual-gate channel region.
Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to significantly reduce undesirable short channel effects that were problematic as the gate length of planar devices was reduced over the years. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior FET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
As FinFET devices have been scaled to meet ever increasing performance and size requirements, the width W of the fins 14 has become very small, e.g., 6-12 nm, and the fin pitch has also been significantly decreased, e.g., the fin pitch may be on the order of about 30-60 nm. Further reductions in these dimensions are anticipated in future product generations. Accordingly, accurately defining these relatively small fin structures can be challenging. One manufacturing technique that is employed in manufacturing FinFET devices is to initially form the trenches 22 in the substrate 12 to define multiple “fins” that extend across the entire substrate 12 in the regions where FinFET devices will be formed, and thereafter remove some of the fins where larger isolation structures will be formed. Using this type of manufacturing approach, better accuracy and repeatability may be achieved in forming the fins 14 to very small dimensions due to the more uniform environment in which the etching process that forms the trenches 22, and thus the fins 14, is performed.
After the fins 14 have been formed, some portion of some of the fins 14 must be removed to create room for or define the spaces where isolation regions will ultimately be formed to separate the individual FinFET devices from one another. As noted above, the fins 14 are typically formed in a regular array. Typically, two separate fin removal or “fin cut” etching processes, involving two different fin-cut masking layers, are performed to remove the unwanted fins (or portions thereof). One of these fin-removal etching processes is sometimes referred to as a so-called “FH cut” process.
The FH cut process involves forming an opening in the mask layer, wherein the long axis of the opening is substantially parallel to the long axis of the fins 14, i.e., the long axis of the opening in the masking layer runs in a direction that corresponds to the gate length direction of the finished FinFET devices (or a direction that is parallel to the long axis of the fins 14). In the FH fin cut process, portions of the axial length of the fins 14 exposed by an FH cut mask (e.g., photoresist) are removed. The FH fin cut process essentially defines the axial length of the active fins 14 that will be positioned above one or more active regions in completed devices. This FH fin cut process is typically an anisotropic cut process.
One such removal technique used for the FH fin cut process is typically referred to as “Fins-cut-First,” as will be described with reference to FIGS. 1B-1F. However, in this process, the portion of the fin to be removed is not actually formed in the substrate. Rather, the patterned fin-formation etch mask 32 is modified such that the underlying substrate material where such a fin portion would otherwise be formed is removed when the fin-formation trenches 22 are etched into the substrate. Accordingly, FIG. 1B depicts a product 30 after a patterned fin-formation hard mask layer 32, e.g., a patterned layer of silicon nitride/silicon dioxide, was formed above the substrate 34 in accordance with the desired fin pattern and pitch. In the depicted example, only a single fin will be removed, i.e., the fin 36 (or portion thereof) that would otherwise correspond to the feature 32A, to make room for an isolation region. However, as will be recognized by those skilled in the art, depending upon the desired final size of the isolation region, portions of more than one fin may be removed using this Fins-cut-First approach.
FIG. 1C depicts the product 30 after a patterned masking layer 38, e.g., a patterned layer of photoresist, was formed above the patterned fin-formation hard mask layer 32. The patterned masking layer 38 has an opening that exposes the feature 32A (for a certain axial length into and out of the drawing page) for removal.
FIG. 1D depicts the product 30 after an etching process was performed through the patterned masking layer 38 so as to remove the portions of feature 32A of the patterned fin-formation hard mask layer 32 that were exposed by the patterned masking layer 38.
FIG. 1E depicts the device 30 after the patterned masking layer 38 was removed and after a fin-formation etching process was performed through the patterned fin-formation hard mask layer 32 (without the feature 32A) so as to define full-depth trenches 40 in the substrate 34 that define the desired fins 36 across the entire substrate. Due to the removal of the desired portion of the feature 32A, the fin-formation etching process removes the portions of the substrate 34 that would have otherwise formed a fin 36 in the area under the removed portions of the feature 32A. One problem with the Fins-cut-First approach is that it inevitably causes variations in fin sizes, i.e., the dimensions 36X and 36Y are different for different fins. This is especially true between fins 36 inside an array of fins and the fins at the edge of the active region that is close to the isolation region. Such variations in fin sizes may lead to unacceptable variations in device performance. Such variations in fin sizes are caused by variable etch loading effects wherein there are different etch rates that result in different etch profiles for the fins 36 due to differing patterning densities, pitch, etc. However, one benefit of the Fins-cut-First approach is that an anisotropic etching process may be performed when forming the trenches 40 since the technique involves removing substantially all of the substrate material where the undesired fin would have otherwise been formed and there is little chance of damaging laterally adjacent fin structures.
FIG. 1F depicts the product 30 after several process operations were performed. First, a layer of insulating material 42, such as silicon dioxide, was formed so as to overfill the trenches 40. Next one or more chemical mechanical polishing (CMP) processes were performed to planarize the upper surface of the insulating material 40 with the top of the fins 36 and thereby remove the patterned fin-formation hard mask 32. Thereafter, an etch-back process was performed to recess the layer of insulating material 42 between the fins 36 and thereby expose the upper portions of the fins 36, which corresponds to the final fin height of the fins 36. Next, a gate structure (not shown) for the product 30 may be formed using either gate-first or gate-last manufacturing techniques.
Another technique employed during the FH cut process is typically referred to as “Fins-cut-Last,” and it will be generally described with reference to FIGS. 1G-1L. FIG. 1G depicts the product 30 after the patterned fin-formation hard mask layer 32 was formed above the substrate 34 in accordance with the desired fin pattern and pitch across all areas of the substrate where FinFET devices will be formed. As before, in the depicted example, only a single fin (or portion thereof) will be removed, i.e., the fin 36 corresponding to the feature 32A, to make room for the isolation region.
FIG. 1H depicts the product 30 after an anisotropic fin-formation etching process was performed through the patterned fin-formation hard mask layer 32 so as to define the full-depth trenches 40 in the substrate 34 that define the fins 36 across the entire substrate in the areas where FinFET devices will be formed. Note that, in the Fins-cut-Last approach, the size of the fins is very uniform, i.e., the dimension 36A is approximately equal to the dimension 36B. This is primarily due to the fact that, in this approach, fins 36 are formed everywhere on the wafer where FinFET devices will be formed in a substantially uniform etch environment, i.e., there is no undesirable etch loading effects to cause variations in fin sizes.
FIGS. 1I-1J depict the device 30 after several process operations were performed. First, a layer of insulating material 44, such as silicon dioxide, was formed so as to overfill the trenches 40. Then a CM′ process was performed to planarize the upper surface of the layer of insulating material 44 with the patterned fin-formation hard mask layer 32. Next, a patterned fin-cut masking layer 46, e.g., a patterned layer of photoresist, was formed above the layer of insulating material 44. The patterned fin-cut masking layer 46 has an opening 46A positioned above the portion of the underlying fin 36 that is to be removed. FIG. 1J is a plan view of the patterned fin-cut masking layer 46 with a generally rectangular-shaped opening 46A that exposes a desired portion of the axial length of the feature 32A of the patterned fin-formation hard mask layer 32 that is to be removed along with the corresponding portion of the axial length of the underlying fin 36.
FIG. 1K depicts the device 30 after one or more anisotropic etching processes were performed to remove the exposed portions of the layer of insulating material 44, the exposed portions of the feature 32A of the patterned fin-formation hard mask layer 32 and the underlying portions of the fin 36. This results in the formation of a trench 45 in the layer of insulating material 44. Typically, as shown in the plan view in FIG. 1J, the trench 45 will take the form of a rectangle that corresponds approximately to the opening 46A in the patterned fin-cut masking layer 46. Inevitably, there will be some inward tapering of the sidewalls of the trench 45. Although not depicted in the drawings, after the trench 45 is formed, the patterned fin-cut masking layer 46 will be removed and additional oxide material (not shown) will be formed through the opening 45A in the trench 45 where the portion of the fin 36 was removed. Then a chemical mechanical polishing (CMP) process will be performed to planarize the upper surface of all of the insulating materials with the top of the patterned fin-formation hard mask layer 32. Thereafter, the isolation regions between devices will be masked and an etch-back process will be performed to recess the layer of insulating material 44 between the fins 36 for each device and thereby expose the upper portions of the fins 36, which corresponds to the final fin height of the fins 36.
There are at least two possible problems with the fins-cut-last approach that generally relate to the size or critical dimension (CD) 45X of the opening 45A of the trench 45. With reference to FIG. 1L, if the CD 45X of the opening 45A is too small, there will typically be some residual portion 36X of the fin 36 remaining at the bottom of the trench 45. If the CD 45X of the opening 45A is increased in an effort to insure complete removal of the unwanted residual fin materials 36X at the bottom of the trench 45, then there is a much greater likeli-hood of damaging the fins 36 adjacent the trench 45 when the fin removal etch process is performed. These issues only get worse as the depth of the trench 45 increases and as packing densities increase.
Some of the aforementioned problems could potentially be remedied by performing a selective isotropic etching process to remove the desired portions of the fin 36 instead of performing an anisotropic etching process. FIGS. 1M-1N depict the device 30 after an isotropic etching process was performed to remove the desired portions of the fin 36 exposed by the opening 46A in the patterned fin-cut masking layer 46. FIG. 1N is a cross-sectional view taken through the long axis of the fin 36 that is cut during the isotropic etching process. One benefit of performing an isotropic fin cut etching process is that, due to the isotropic nature of the process, any undesirable residual fin material 36X (see FIG. 1L) at the bottom of the trench 45 may be eliminated. As shown in FIG. 1N, performing an isotropic fin-removal etching process results in the formation of a small trench 48 in the substrate 34. Typically, only a portion of the entire axial length of the fin 36 will be removed as other portions of the initially formed fin 36 will serve as permanent fins 36A for other FinFET devices. Due to the isotropic nature of the fin removal etching process, the cut ends 50 of the permanent fins 36A that are adjacent the portion of the fin 36 that was removed may be subjected to relatively severe undercutting, as depicted in FIG. 1N. That is, due to the nature of an isotropic etching process, there may be some undesirable loss of the fin material in the directions indicated by the arrows 47 in FIG. 1J.
As it relates to the formation of FinFET devices, the number of fins of a FinFET device is an important consideration. In general, a FinFET device with a greater number of fins tends to exhibit greater performance, i.e., drive current, than a FinFET device with a lesser number of fins. Accordingly, all other things being equal, a FinFET device with a relatively greater number of fins would be a candidate for various high performance applications, such being included as part of a critical path for a logic circuit on an integrated circuit product. On the other hand, FinFET devices with a lesser number of fins may be more suitable for applications involving less relative power consumption, as such FinFET devices tend to exhibit relatively lower off-state leakage currents. Accordingly, such FinFET devices may be employed in non-critical path circuits where power consumption and power management is an important factor.
In general, there are two different ways that may be employed in an attempt to produce FinFET devices with different numbers of fins. Historically, FinFET devices have been formed in and above active regions that have a rectangular configuration. FIG. 1O is a simplistic depiction of one illustrative example of how different FinFET devices, each having a different number of fins, may be formed above spaced-apart active regions that have a rectangular configuration. As shown therein, the product is comprised of a plurality of fins 36, a plurality of dummy gates 52 and a plurality of active gates 54. First and second FinFET devices 56, 58 (each of which are two-fin devices) are formed in and above spaced-apart rectangular active regions 60, 62, respectively. FIG. 1O also depicts first and second FinFET devices 64, 66 (each of which are three-fin devices) formed in and above spaced-apart rectangular active regions 68, 70, respectively. Such a configuration does result in a plurality of FinFET devices 56, 58, 64 and 66 having a different number of fins. However, each of the FinFET devices are formed above spaced-apart, rectangular shaped active regions 60, 62, 68 and 70, respectively. One positive aspect of the embodiment shown in FIG. 1O is that there is little or no undercutting of the cut end surface 50 of the fins, as described in FIGS. 1M-1N above (see surface 50 in FIG. 1N). One negative aspect of the approach depicted in FIG. 1O, is that there is a relatively significant area penalty (e.g., 10-20%) associated with forming the four spaced-apart, rectangular active regions 60, 62, 68 and 70.
FIG. 1P depicts another illustrative way wherein FinFET devices may be formed with a different number of fins. In this embodiment, so-called “tapered” FinFET devices 80, 82 are formed in and above substantially non-rectangular shaped active regions 84, 86, respectively, wherein the substantially non-rectangular active area occupies less area than that of a normal four-sided rectangle of similar dimensions. This definition of “tapered devices” and “substantially non-rectangular shaped active regions” shall be used in the specification and throughout the claims. The term “substantially” is employed as part of the definition so that precise geometric precision with respect to the configuration of the non-rectangular shaped active regions is not required due to the variabilities that may be encountered when performing etching processes to define the active regions.
At the bottom of FIG. 1P, one example of the substantially non-rectangular shaped active region 86 is shown by itself so as to clearly show its substantially non-rectangular configuration when viewed from above. A FinFET device formed above a substantially non-rectangular shaped active region (as opposed to a traditional rectangular shaped active region) may be generally referred to as a “tapered” FinFET device, in that the substantially non-rectangular shaped active region is configured or tapered (i.e., substantially non-rectangular) so as to allow formation of FinFET devices (with different numbers of fins) above that tapered, substantially non-rectangular shaped active region. In the depicted example, each of the tapered FinFET devices 80, 82 include a two-fin FinFET device and a three-fin FinFET device. Such tapered FinFET devices offer significant scaling benefits as compared to the traditional FinFET devices shown in FIG. 1O that are formed above the spaced-apart traditional rectangular active regions 60, 62, 68 and 70.
After the fins are cut, and the isolation regions are formed, the gate structures are then formed across the fins. In the case where a replacement gate process is used to manufacture the FinFET devices, the initial gate structures are sacrificial gate structures that will subsequently be removed and replaced with final gate structures for the devices. Several process operations are performed after the formation of the sacrificial gate structures, e.g., the formation of epi semiconductor material in the source/drain regions of the device. When the epi semiconductor material is formed in the source/drain regions, it is important that the epi material not form in unwanted areas of the devices so as to not create a multitude of problems, e.g., growing around the end of a gate structure so as to create a short circuit between the source region and drain region, bridging the space between two adjacent active regions, etc. Thus, with reference to FIG. 1Q, when the fins are cut, the cut is located such that the cut ends of the fins will be positioned under the dummy gate structures when they are formed. This is sometimes referred to as the fins being “tucked” in the sense that the cut end of the fin is positioned under or “tucked under” the dummy gate structure. Such a tucked fin arrangement is required on many modern integrated circuit products so as to prevent the undesirable formation of epi semiconductor material in undesirable places and to produce uniform source/drain regions (when the epi material is formed) for all of the devices so as to avoid variances in device performance.
FIG. 1R is an idealized depiction of a tapered device 80 that is formed above a substantially non-rectangular active area 84. As depicted, all of the fins 36 are properly tucked under a gate structure 52, as indicated in the dashed line regions 55. However, in fabricating a real-world device using a single mask to define the substantially non-rectangular active area 84 and the fins 36, there is unavoidable corner rounding 85 of a portion of the active region 84, as shown in FIG. 1S. As a result of this corner rounding, the fin 36A is axially shorter than intended, while the fin 36B is axially longer than intended. The net result is that when the gate 52 (shown in dashed lines) is formed, the fins 36A and 36B will not be properly tucked under the gate 52. More specifically, the fin 36A will be short of the gate 52 (as depicted in the dashed line region 87), while the fin 36B will extend beyond the gate 52 (as depicted in the dashed line region 89). As a result of the foregoing, the untucked portions of the fins 36A, 36B can serve as sites for undesirable epi growth when epi material is formed in the source/drain regions of the FinFET devices.
To eliminate the above-described problem of corner rounding 85 of the substantially non-rectangular active area 84 for tapered devices, two separate masking layers can be used when defining the fins 36 in the substrate. In the two-mask layer approach, the separately formed FH mask and the FP mask are formed such that they overlap so as to define an essentially right-angle corner in the area where the corner rounding 85 occurs when the single masking layer approach is used. However, even when the double mask approach is used, when an isotropic etch process is performed in the fin cut last process to remove the undesirable portions 36X of the fins 36 (see FIGS. 1L-1N), there will still be some undesirable undercutting (like the cut ends 50 shown in FIG. 1N) of the fins for the tapered device. On the other hand, performing a fin-cut-first process avoids the problem of undercutting of the fins for the tapered device, but, as noted above, the fin-cut-first process can lead to undesirable variations in the dimensions of the fins which can adversely affect the performance of some devices, such as those devices in high-performance areas like logic circuits or SRAM circuits, etc.
The present disclosure is directed to various hybrid fin cut etching processes for integrated circuit products that include both tapered and non-tapered FinFET semiconductor devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.